1. Field of the Invention
The present invention relates to a multi-layered interconnection structure in which interconnections and plugs are provided in the form of damascene and a manufacturing method thereof.
2. Description of the Related Art
In recent years, as the LSI (Large Scale Integrated Circuit) achieves a still more densely spaced arrangement, techniques to form a multi-layered interconnection with a three-dimensional interconnection structure have been acquiring further importance. In the process flow of manufacturing a multi-layered interconnection, every step of depositing and working a metal, depositing an insulating film and applying planarization thereto, and forming a through hole and damascening by inlaying a metal therein must be performed at a temperature below the heat-proof temperature of each metal material. Moreover, the actual process must be designed to have simple and practical steps, while paying, at the same time, due regard to the yield and reliability of the final product thereby.
Meanwhile, in order to satisfy demands that the element should have a still higher speed, low-resistance materials such as copper have become in wide use. With copper, however, patterning by means of etching is difficult to perform. Therefore, when copper is used, an interconnection must be formed by a method different from the conventional method used for forming an Al interconnection.
Under such circumstances, extensive investigations are currently conducted over matters concerning a method of forming a damascene-type multi-layered interconnection that meets specific requirements of a new interconnection material such as copper.
Now, referring to FIGS. 8 to 12, a conventional method of forming a copper damascene interconnection structure is described herein below.
First, a lower layer interconnection is formed as follows.
After a metal film 1 is formed on a semiconductor substrate (not shown in the drawings), a plasma SiO2 film 2 (100 nm in thickness), a HSQ (Hydrogen Silisesquioxane) film 3 (400 nm in thickness), a plasma SiO2 film 4 (100 nm in thickness), a HSQ film 5 (400 nm in thickness) and a plasma SiO2 film 6 (200 nm in thickness) are formed thereon in this order (FIG. 8(a)). A photoresist 7 patterned into a prescribed shape is then formed over that (FIG. 8(b)). Using this photoresist 7 as a mask, dry etching is applied thereto so as to form a trench that reaches the metal film 1 (FIG. 8(c)). After that, a strip treatment of the photoresist 7 is carried out by means of ashing with the oxygen plasma and cleaning with a stripper containing amines. Next, a photoresist 7xe2x80x2 having a wider opening than the width of this trench is formed (FIG. 8(d)), and another dry etching is applied thereto, using this photoresist 7xe2x80x2 as a mask, and thereby a sectionally partially T-shaped trench is formed (FIG. 9(a)).
After removing the photoresist 7xe2x80x2 (FIG. 9(b)), a barrier metal film 8 (50 nm in thickness) made of TiN is deposited over the entire surface by the sputtering method (FIG. 9(c)). Further, over that, a seed film (not shown in the drawings) for the purpose of performing electroplating with copper is deposited to a thickness of 100 nm by the sputtering method, and thereon a copper film 10 (1000 nm in thickness) is grown by electroplating so as to fill up the trench section (FIG. 9(d)). Subsequently, portions of the copper film 10 as well as the barrier metal film 8 which are formed in a region other than the trench section are removed by the CMP (Chemical Mechanical Polishing) and thereby a lower layer interconnection is accomplished (FIG. 10(a)).
Over this lower layer interconnection, a SiN film 20 is formed by the plasma CVD (Chemical Vapour Deposition) method (FIG. 10(b)). This SiN film 20 serves as an etching stopper when a through hole between the lower layer and the upper layer interconnections is formed as described below. With the SiN film 20 being set, degradation of the lower layer interconnection at the time of formation of the through hole can be suppressed to a certain degree. Further, the SiN film can prevent metal particles of copper and the like from diffusing into an interlayer insulating film and giving adverse effects on the element. The film thickness of the SiN film 20 is normally 50 nm or so.
Next, an upper layer interconnection is formed in the similar way as the formation of the lower layer interconnection. A HSQ film 13 (400 nm in thickness), a plasma SiO2 film 14 (100 nm in thickness), a HSQ film 15 (400 nm in thickness) and a plasma SiO2 film 16 (200 nm in thickness) are formed in this order. A photoresist 17 patterned into a prescribed shape is then formed over that (FIG. 11(a)).
Using this photoresist 17 as a mask, dry etching is applied thereto. At this, owing to a difference in etching rate between the HSQ film 13 and the SiN film 20, the etching is stopped at the top section of the SiN film 20 (FIG. 11(a)). Following this, together with strip of the photoresist 17, the deposit produced by etching is removed, by means of ashing with the oxygen plasma and cleaning with a stripper. After that, a photoresist 17xe2x80x2 having a wider opening than the width of this trench is formed, and another dry etching is performed, using this photoresist 17xe2x80x2 as a mask, and thereby a sectionally partially T-shaped trench is formed (FIG. 11(b)). Next, the photoresist 17xe2x80x2 as well as the etching deposit produced by etching are removed by means of oxygen plasma ashing and cleaning with a stripper. Next, the SiN film 20 is etched by dry etching, which exposes the copper film 10 (FIG. 11(c)). After that, cleaning with a stripper is again applied thereto and the etching deposit produced by this dry etching or the deposit of SiN origin is removed.
A barrier metal film 18 (50 nm in thickness) and a copper film 19 (1000 nm in thickness) are formed in this order so as to fill up completely the trench section which is formed as described above, and thereby the trench section is damascened. Subsequently, carrying out the planarization by the CMP, the multi-layered interconnection structure as shown in FIG. 12 is formed.
In the conventional technique describe above, a SiN film is formed over the lower layer interconnection with the object of providing an etching stopper film as well as suppressing diffusion of copper or the like. However, considering the following adverse points given by this film, further improvements yet remain to be made.
Firstly, the parasitic capacitance between interconnections on the same interconnection layer becomes considerably large owing to the fringe effect. FIG. 14 is a diagram to explain this phenomenon. Between the adjacent interconnections 50 and 51 at the same interconnection layer, there are present s parasitic capacitor 52 in which a SiO2 film 54 serves as a dielectric film and a parasitic capacitor 53 in which a SiN film 55 serves as a dielectric film. Since the permittivity of the SiO2 film is comparatively low, the effect of the parasitic capacitor 52 is relatively small. The permittivity of SiN is, however, approximately twice as much as that of SiO2 so that the parasitic capacitor 53 has a large capacitance. In short, the presence of this parasitic capacitor 53 makes a cross talk between the interconnections 50 and 51 liable to happen.
Secondly, there are known to be problems such as degradation of the lower layer interconnection and contamination of the through hole which are apt to take place in the step of removing the SiN film. For the SiN film is an insulating film, the SiN film within the through hole must be removed. The removal of the SiN film is carried out by means of dry etching and, on that occasion, the deposit of SiN origin produced by this etching should be cleared off as well. Although the removal of the deposit of SiN origin can be normally made using a stripper for resist, this tends to cause degradation of the underlying interconnection, in turn. While copper, which has a low resistivity, is generally used as the interconnection material, a stripper that can remove the deposit of SiN origin without degrading copper has not be found yet. Consequently, it is hard to remove the above deposit without causing degradation of the copper surface.
Further, to simplify the steps in the manufacturing process, there may be employed a method in which the SiO2 film and the SiN film are dry etched at once in the same step. In this instance, at the time of overetching performed to remove SiN thoroughly, the underlying lower layer interconnection is also etched. This degrades the surface of the lower layer interconnection and, in addition, gives rise to another problem that the etching deposit resulting from this etching is attached to the inside wall of the hole. The main component of this etching deposit is a substance produced by a reaction of the metal material constituting the lower layer interconnection and the etching gas and very difficult to remove by any normal method of cleaning. Yet, if the etching deposit of this sort remains, it brings about problems such that the leakage current may flow in the interlayer insulating film and an element formed under the interlayer insulating film such as a transistor may make an error operation.
Further, in the case that the deposit of SiN origin or the etching deposit is left in the through hole, the contact metal resistance may become extremely high and stop the current flow.
As described above, setting the SiN film itself causes various problems.
However, if an etching stopper such as SiN is not set therein at all, the lower layer interconnection becomes exposed on the occasion of dry etching while forming a through hole as well as on the occasion of ashing and a wet treatment in the step of removing a mask so that the surface thereof becomes heavily degraded.
In light of the above problems, an object of the present invention is to provide a multi-layered interconnection structure of high quality, wherein neither parasitic capacitor due to the fringe effect is brought about nor degradation of the lower layer interconnection or contamination of the through hole takes place.
In accordance with an aspect of the present invention, there is provided a semiconductor device, comprising:
a metal interconnection set on a semiconductor substrate; and
a via plug formed to connect with the upper surface of said metal interconnection;
outlines of said metal interconnection being covered with a barrier metal film.
Because outlines of the metal interconnection of this semiconductor device are covered with a barrier metal film, the metal interconnection hardly suffers damage in the manufacturing steps and, thus, shows excellent characteristics. Further, in this semiconductor device, when a through hole for the plug is formed onto the metal interconnection, the etching deposit difficult to remove can be effectively prevented from being produced.
This solves such problems as the leakage current may flow in an interlayer insulating film and an element formed under the interlayer insulating film such as a transistor may make an error operation. Furthermore, an increase in contact metal resistance that occurs if the etching deposit is left in the through hole can be avoided.
Here, a structure in which outlines of a metal interconnection are covered with a barrier metal film is illustrated in FIG. 1. As shown in the drawing, a metal interconnection 111 is covered with a barrier metal film 110. As used in the present invention, a structure in which xe2x80x9coutlines of a metal interconnection are covered with a barrier metal filmxe2x80x9d, refers to a structure in which all sides of the metal interconnection, that is, the upper and lower surfaces and all lateral faces thereof are all covered with a barrier metal film 110, as shown in the drawing. In the conventional interconnection structure, as shown in FIG. 13, the upper surface of a metal interconnection 31 is not covered with a barrier metal film 30, and an etching film 32 made of a SiN film or the like is formed thereon instead. This results in the very problem that damage to the metal interconnection 31 or contamination of a through hole formed thereto may be brought about in the steps of manufacturing the multi-layered interconnection. In contrast with this, in the present invention, the upper surface of the metal interconnection is also covered with a barrier metal film so that a problem of this sort can be eliminated. Further, with the structure in which outlines thereof are covered with a barrier metal film, metal such as copper can be effectively prevented from diffusing into an interlayer insulating film.
Further, in accordance with an aspect of the present invention, there is provided a semiconductor device having a plurality of interconnection layers on a semiconductor substrate;
one of said interconnection layers comprising a plurality of metal interconnections with various line widths and a plurality of via plugs formed to connect with the upper surface of said plural metal interconnections;
outlines of said plural metal interconnections being covered with barrier metal films.
Normally, in a multi-layered interconnection structure, a plurality of metal interconnections with various line widths are formed within one of the interconnection layers (FIG. 16). It is preferable that these plural metal interconnections each have a structure in which outlines of each are individually covered with a barrier metal film. With this arrangement, damage to the metal interconnections in the manufacturing steps can be effectively avoided, and metal interconnections and thorough plugs, both having excellent characteristics, can be obtained. That is, by covering outlines of metal interconnections having various line widths with respective barrier metal films, as described above, damage to the metal interconnections in the manufacturing steps can be avoided and contamination of thorough holes for plugs, prevented.
The structure in which outlines of a plurality of metal interconnections with various line widths that are laid within one of the interconnection layers are individually covered with respective barrier metal films can be obtained only by a novel manufacturing process that differs from the conventional damascene process. In the present invention, the above structure is accomplished by employing a recess formation technique described below.
Further, in the above semiconductor device, though it is preferable to have a structure in which, among a plurality of metal interconnections having various line widths, all or the majority thereof are covered with barrier metal films, it is possible to have a structure in which only a part thereof are covered with barrier metal films.
Further, in accordance with an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of:
forming a caved-in section at a prescribed position in a first interlayer insulating film laid on a semiconductor substrate;
forming a first barrier metal film over the entire surface and thereafter forming a first conductive film so as to fill up said caved-in section completely in substance;
forming a recess by removing an upper section of the first conductive film that fills said caved-in section, together with removing a portion of the first conductive film formed in a region other than said caved-in section;
forming a second barrier metal film over the entire surface so as to fill up the recess;
removing portions of the first barrier metal film and the second barrier metal film which are formed in a region other than said caved-in section;
forming a second interlayer insulating film over the entire surface;
forming, in the second interlayer insulating film, a through hole that reaches the second barrier metal film; and
forming a second conductive film so as to fill up said through hole.
In this method of manufacturing a semiconductor device, a recess is formed by removing an upper section of the first conductive film that fills the caved-in section and then a second barrier metal film so as to fill up the recess, and thereafter portions of the first barrier metal film and the second barrier metal film which are formed in a region other than the caved-in section are removed. By way of these steps, a metal interconnection whose outlines are covered with a barrier metal film can be formed fittingly. After the metal interconnection with such a structure is formed, a through hole and an upper layer interconnection are formed thereon so that the metal interconnection hardly suffers damage in the manufacturing steps. Therefore, a metal interconnection having excellent characteristics can be obtained. Further, a through hole formed onto this metal interconnection is hard to receive metal contamination in the manufacturing steps, thus achieving high quality.
In the present invention, in forming a metal interconnection with a structure in which outlines thereof are covered with a barrier metal film., a means of forming a recess is utilized. That is, after a first conductive film is formed so as to fill up the caved-in section completely in substance, a recess is formed by removing an upper section of the first conductive film and then a second barrier metal film is formed in the part of this recess, and thereby the structure mentioned above is formed. The term xe2x80x9ca recessxe2x80x9d refers to a sunken section having a form shown in FIG. 4(a) and it takes the configuration of a lower step as against other regions. By forming such a recess, the above structure can be achieved for certain regardless of the geometry of the caved-in section. Further, this method allows to cover individual outlines of a plurality of metal interconnections having various line widths that are laid within one of the interconnection layers with respective barrier metal films simultaneously in one and the same step.
As described above, in the present invention, after a first conductive film is formed so as to fill the caved-in section completely in substance, a recess is formed by removing a section of the first conductive film. At this, it is also possible to form a shape resembling a recess by reducing the film thickness of the first conductive film. FIG. 15 illustrates such a step. First, after a partially T-shaped trench is formed in an interlayer insulating film 40, a barrier metal film 41 and a conductive film 42 are formed so as to fill up this trench in the form of damascene (FIG. 15(a)), and then, by performing the CMP, a dishing section 43 resembling a recess is formed (FIG. 15(b)). However, in this method, the shape of the damascene section tends to reflect the original shape of the caved-in section and to become dishing-shaped with the edge sections being upraised. The dishing basically differs from the recess and, unlike the recess, its upper surface cannot be covered with a barrier metal film and, in consequence, the effects of the present invention cannot be obtained. Further, with the technique described above, it is extremely difficult to cover a plurality of caved-in sections having various line widths that are laid within the identical interconnection layer with respective barrier metal films simultaneously in one and the same step. This owes to a fact that, if respective metal films are inlaid, in the form of damascene, into a plurality of caved-in sections having various line widths, there are left two sets of trenches, one in which a recess or a form resembling a recess is formed and the other in which neither is formed (FIG. 17).
Accordingly, the formation of a recess with the object of covering the upper surface of the metal interconnection with a barrier metal is preferably carried out in the step wherein a first conductive film is first formed so as to fill up the caved-in section completely in substance and thereafter an upper section of the first conductive film is removed.
As described above, in the present invention, since outlines of a metal interconnection is covered with a barrier metal film, the metal interconnection hardly suffers damage in the step of forming a through hole. Moreover, the through hole formed onto the metal interconnection is hard to receive metal contamination in the manufacturing steps. In consequence, a multi-layered interconnection structure having excellent characteristics can be obtained.